AMD Zen 6: 12 cores and 48 MB L3 cache per chiplet

AMD has revealed details about its upcoming Zen 6 architecture, which will allow a single chiplet to house 12 performance cores and 48 MB of L3 cache, potentially enabling 24-core desktop processors using two chiplets. This marks a significant increase from the current Zen 5 design, which supports up to 8 cores and 32 MB of L3 cache per chiplet. The new architecture, set to power future EPYC Venice server processors and likely next-generation Ryzen desktop CPUs, also delivers an approximate 27% improvement in instructions per clock (IPC) in server and AI workloads. AMD has enhanced branch prediction, increased the execution queue to 6,750 operations, and improved recovery from mispredictions, which could benefit gaming performance by reducing latency and wasted work. For the Ryzen X3D line, the single-chiplet design with 12 cores could be paired with 96 MB of 3D V-Cache, totaling 144 MB of L3 cache, simplifying thread scheduling compared to current dual-chiplet models. The server chips will use TSMC's 2nm N2P process, though AMD has not yet confirmed specifications for consumer Ryzen models.